In recent years, research and development of nonvolatile memory devices having memory cells each including a variable resistance element has been in progress. The variable resistance element refers to an element that has a nature of changing its resistance value according to an electrical signal and can store information depending on the change in resistance value.
For implementing memory cells each including a variable resistance element, a so-called cross point structure may be adopted as an example. In the cross point structure, memory cells are formed at intersections of bit lines and word lines placed orthogonal to each other so as to be sandwiched between the bit lines and the word lines.
Patent Document 1 describes a nonvolatile memory device using variable resistors having bidirectionality as memory cells. In this document, disclosed is use of a varistor, for example, as a bidirectional nonlinear element for a diode of a memory cell for the purpose of reducing the leak current flowing in a non-selected cell. The cross point structure is also disclosed.
Patent Document 2 describes a nonvolatile memory device provided with a three-dimensional cross-point variable-resistance memory array having a multilayer structure.
Non-Patent Document 1 discloses a memory cell structure in which a variable resistance film and a unidirectional diode are combined. A multilayer structure is also disclosed.
Patent Document 3 discloses a nonvolatile memory having a three-dimensional structure that includes memory cells each having a polycrystalline silicon diode and a unipolar rewritable variable-resistance memory element (RRAM).
Patent Document 4 discloses a multilayer memory structure having memory cells each composed of a bipolar rewritable variable-resistance memory element and a zener diode.
Patent Document 5 discloses a multilayer memory structure having memory cells each composed of a memory element and a unidirectional control element.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2006-203098 (FIGS. 2 and 5)    Patent Document 2: Japanese Laid-Open Patent Publication No. 2005-311322 (FIG. 4)    Patent Document 3: Japanese Laid-Open Patent Publication No. 2007-165873    Patent Document 4: Japanese National Phase PCT Laid-Open Patent Publication No. 2006-514393    Patent Document 5: Japanese Laid-Open Patent Publication No. 2004-31948    Non-Patent Document 1: I. G. Baek et al., “Multi-layer Cross-point Binary Oxide Resistive Memory (OxRRAM) for Post-NAND Storage Application,” IEDM2005 (IEEE International Electron Devices Meeting 2005), 769-772, Session 31 (FIG. 7, FIG. 11), Dec. 5, 2005